Silicon Graphics International hopes by 2018 to build supercomputers 500 times faster than the most powerful today, using specially designed accelerator chips made by Intel, SGI's chief technology officer said.
SGI hopes to bring a massive performance boost to its supercomputers through highly parallel processors based on Intel's MIC (many integrated cores) architecture, said Eng Lim Goh, CTO at SGI. In conjunction with Xeon server CPUs, the MIC chips will run millions of threads in parallel, which will help scale supercomputer performance.
Chips based on the MIC architecture mix standard x86 cores with specialized cores to boost high-performance computing. Today's fastest supercomputers top out at around 2.5 petaflops (2.5 thousand trillion calculations per second), but efforts to improve throughput and on-chip performance are under way. IBM, for example, said it will use pulses of light to accelerate data transfers between chips. These and other measures could lead to supercomputers that can deliver performance of over one exaflop, or 1000 petaflops, by 2020.
Standard x86 CPUs will need accelerators like Intel's MIC chips to achieve faster performance, Goh said.
"[MIC] gives us the compute density we need" to get to deliver exaflops of performance by 2018, Goh said.
Accelerators such as graphics processors (GPUs) are currently being used with CPUs to execute more calculations per second, Goh said. While some accelerators achieve desired results, many are not satisfied with the performance related to the time and cost spent porting applications to work with accelerators.
Intel's MIC architecture will address that problem by including many specialized cores in a chip able to run standard x86 software.
The MIC architecture is viewed as Intel's answer to GPUs from companies like Nvidia and Advanced Micro Devices, which pack hundreds of computing cores. The world's fastest supercomputer, the Tianhe-1A supercomputer in China, incorporates thousands of Intel CPU cores and Nvidia graphics chips to reach a sustained performance of 2.5 petaflops, and peak performance of 4.7 petaflops.
Intel showed its first experimental MIC chip, code-named Knights Ferry, in June last year. The chip sits in a PCI-Express slot. It has 32 cores and combines vector processing units with standard CPU cores. Though not commercially released, chip samples have shipped out in small numbers to organizations now writing programs around the architecture.
A Xeon server with eight Knights Ferry chips can deliver 7.4 teraflops of performance, said John Hengeveld, director of marketing for Intel's Data Center Group.
In the pipeline is Intel's first commercial MIC chip, code-named Knights Corner, with more than 50 cores. Hengeveld declined to provide a shipping date for Knights Corner, but said the chip will be made using the 22-nanometer manufacturing process. The current Knights Ferry chip is made using the 45-nm process.
Sign up for Computerworld eNewsletters.