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Imagination adds safety, resilience to processor for IoT

Peter Sayer | June 15, 2017
If your industry requires components to be 'functionally safe,' Imagination has a high-powered processor for you.

Mobileye uses MIPS cores in the EyeQ 4 system-on-chip (SoC) devices it develops for auto manufacturers to provide automated driver assistance systems such as lane keeping or adaptive cruise control.

Last year, it said it would use Imagination's MIPS I6500 core in its EyeQ 5 SoCs intended to support autonomous driving. The I6500 is a 64-bit multicore design in which the cores can run at different speeds ("heterogeneous inside," as Imagination puts it) and which can easily connect to GPUs and other application-specific accelerators ("heterogeneous outside").

There was just one hitch: There was no guarantee that it would be functionally safe, a must in the safety-conscious automobile industry.

Now, though, Imagination has overhauled the design. A new version, the I6500-F, contains additional transistors to flag errors in data transmission and storage, and to perform regular self-test operations on processor cores in a way that doesn't affect operation.



Chip designers that are able to support functionally safe design methodologies can help device makers get their products on the market quicker.

"There are some changes to the 6500 to make it the F, but these changes don't change the functionality of the design," said Tim Mace, Business Development Manager for MIPS and Imagination. "It runs the same software and integrates with accelerators in the same way."

The main benefit of the new version, he said, is the level of compliance with ISO 26262, but there's also some additional logic, largely transparent to the user, that is able to report errors when it finds them.

"Even if your silicon does exactly what you intended it to do, it can still change over time. For example, it can just wear out. Or you can get some random errors, for example from solar radiation or background radiation. A bit could change. You need some resilience to spot these errors when they occur and some mechanism to make sure it fails safe or recovers gracefully."

That resilience comes from the incorporation of parity checks and logic for built-in self-testing. In a multi-core processor design like the I6500, that could involve repeatedly moving processes to a known-good core, and self-testing the now-vacant core to be sure it too is safe.

"In automotive there is a requirement that if an error occurs, you need to detect it within a certain period of time. We need to repeat these checks in the background to continuously check if an error has crept in," said Mace.

The extra logic increases the die size of the chip by less than 10 percent, and will entail a slight increase in cost, but that could be a small price to pay for a "thing" that stays on the internet -- or the road -- even when the unexpected happens.


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