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Today's NAND flash has hit a development dead-end

Lucas Mearian | Aug. 6, 2015
The NAND flash technology that Toshiba introduced in 1989, making thumb drives, SSDs and your smartphone's memory possible, has finally reached a development dead end.

Micron's and Intel's 32-layer 3D NAND will focus on cutting costs and increasing capacities, while their new 3D XPoint RAM will replace some DRAM and NAND flash for high-performance applications, such as big data analytics.

Intel and Micron heralded 3D XPoint RAM as "the first new class of memory since 1989," referring to floating gate NAND.

3D XPoint, a type of resistive memory that doesn't store an electrical charge, will sport 1,000 times the performance and endurance of planar NAND flash. As far as endurance, it can handle about one million erase-write cycles, meaning the new memory would last pretty much forever. Today's planar NAND sports 3,000 to 10,000 erase-write cycles.

So dense is the XPoint RAM, that for data centers, Intel will be able to fit 1TB on a card just two millimeters thick.

3D XPoint technology is a new class of non-volatile memory that relies on resistance change of the bulk material to achieve non-volatility. Unlike Phase Change Memory, 3D XPoint technology uses a cross-point (XPoint) architecture -- like a 3D lattice -- enabling it to scale in ways that Phase Change Memory can't, Intel said. Unlike Memristors -- another type of resistive memory -- 3D XPoint technology uses the bulk material to switch resistance state and does not rely on statistically variable filaments, enabling it to reach manufacturing.

The combination of architecture and the unique materials in both the memory cell and a selector that enables reads and writes enable 3D XPoint technology to achieve higher density and better performance and endurance.

So why not replace 3D NAND with 3D XPoint memory? It's too expensive to produce,  Intel has said. Because of its price point, 3D XPoint memory will reside between DRAM, which is faster but more expensive, and 3D NAND, which is cheaper but slower.

With all these new non-volatile memories popping up, planar NAND cannot compete on scale. But, it has had quite a run from the days when it was 130nm in size (in 1989), or even 40nm (in 2006).

Consider this. A strand of human DNA is 2.5 nanometers in diameter, and there are 25,400,000 nanometers in one inch. Now consider that major NAND flash memory makers are mass producing NAND using 15nm and 16nm-sized lithography. That just doesn't leave much room left to further shrink it.

So at the same time manufacturers been shrinking planar NAND process technologies, they've been increasing the number of bits of data the memory can store per transistor or cell. They've moved from one bit in single-level cell (SLC) NAND, to two bits in multi-level cell (MLC) NAND, to three bits in triple-level cell (TLC) NAND.


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